Structure with self aligned resist layer on an interconnect surface and method of making same

ABSTRACT

A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

FIELD OF THE INVENTION

The present invention relates generally to an interconnect structure andmethod of fabricating the same and, more particularly, to a structurewith a self-aligned resist layer on a surface of the interconnects foruse in forming dielectric sub-structures such as air gaps in aninsulator material between the interconnects, and method of fabricatingthe same.

BACKGROUND

To fabricate microelectronic semiconductor devices such as an integratedcircuit (IC), many different layers of metal interconnects and theirsurrounding insulation are deposited and patterned above the transistorlayer on a silicon wafer. The insulation layers may be, for example,silicon dioxide, silicon oxynitride, fluorinated silicate glass (FSG),organosilicate glass (OSG, SiCOH), and the like. These insulation layersare deposited between the metal interconnect layers, i.e., interleveldielectric (ILD) layers, and may act as electrical insulationtherebetween.

The metal interconnect layers are interconnected by metallizationthrough vias etched in the intervening insulation layers. Additionally,interconnects are provided separately within the dielectric (insulation)layers. To accomplish this, the stacked layers of metal and insulationundergo photolithographic processing to provide a pattern consistentwith a predetermined IC design. By way of example, the top layer of thestructure may be covered with a photo resist layer of photo-reactivepolymeric material for patterning via a mask. A photolithographicprocess using either visible or ultraviolet light is then directedthrough the mask onto the photo resist layer to expose it in the maskpattern. An antireflective coating (ARC) layer may be provided at thetop portion of the wafer substrate to minimize reflection of light backto the photo resist layer for more uniform processing. Regardless of thefabrication process, to maximize the integration of the devicecomponents in very large scale integration (VLSI), it is necessary toincrease the density of the components.

Although silicon dioxide material has been used as an insulatingmaterial due to its thermal stability and mechanical strength, in recentyears it has been found that better device performance may be achievedby using a lower dielectric constant material. By using a lowerdielectric constant insulator material, a reduction in the capacitanceof the structure can be achieved which, in turn, increases the devicespeed. However, use of organic low-k dielectric material such as, forexample, SiCOH, tends to have lower mechanical strength thanconventional dielectric materials such as, for example, silicon oxide.

By building a device having a low-k dielectric or a hybrid low-kdielectric stack, the large intra-level line-to-line component of wiringcapacitive coupling is reduced, thus maximizing the positive benefit ofthe low-k material while improving the overall robustness andreliability of the finished structure. The hybrid oxide/low-k dielectricstack structure is much more robust than an “all low-k” dielectricstack, but with a concomitant increase in wiring capacitance relative tothe all low-k stack. As insulator dielectric constants continue to bedecreased, for example by adding porosity to the low-k material such asSiCOH, the overall dielectric mechanical strength continues to decreaseas well.

Nonetheless, even with the lower dielectric constant materialsincluding, for example, a hybrid oxide/low-k dielectric stack structure,there is still the possibility to improve even further the electricalproperties of the device by lowering the effective K (K_(eff)) of amultilevel structure or a K of the dielectric material by forming voidedchannels (conventionally referred to as “air gaps”, though they may notcontain air) within the dielectric material between the interconnectsand vias. The channels are vacuum filled and have a dielectric constantof about 1.0, and represent a dielectric sub-structure between the metalinterconnects in the IC. By using such channels, the Keff of a higherdielectric constant insulator may be lowered significantly withoutreducing its mechanical strength by nearly as much.

There may be additional reasons for creating other types of dielectricsub-structures between the metal interconnects. For example, porousultralow-k insulator surfaces may need to be strengthened or repairedafter chemical-mechanical polishing or plasma precleans prior to capdepositions, to improve their time dependent dielectric breakdown (TDDB)reliability. Similar to the air gap process, this might requiresub-lithographic patterning to define regions where sub-structureprocesses are effective.

In known systems, sub-resolution lithography processes have been used tocreate such channels. This typically consists of new manufacturingprocesses and tool sets which add to the overall cost of the fabricationof the semiconductor device. Also, in sub-resolution lithographyprocesses, it is necessary to etch wide troughs in empty spaces which,in turn, cannot be pinched off by ILD PECVD deposition. Additionally,although the channels create low line-line capacitance, there remains ahigh level-level capacitance for wide lines. This, of course, affectsthe overall electrical properties of the device. Also, air gaps canoccur near the vias from a higher level which creates the risk ofplating bath or metal fill at these areas. Lastly, in known processes,there is also the requirement of providing an isotropic etch which mayetch underneath the interconnect thus leaving it unsupported or floatingand, thus degrading the entire structural and electrical performance ofthe device.

Accordingly, there exists a need in the art to overcome the deficienciesand limitations described hereinabove.

SUMMARY

In a first aspect of the invention a non-lithographic method comprisesapplying a resist on a structure comprising at least one ofinterconnects formed in an insulator material. The method furtherincludes blanket-exposing the resist to energy and developing the resistto expose surfaces of the insulator material while protecting theinterconnects. The method further includes forming air gaps in theinsulator material by an etching process, while the interconnects remainprotected by the resist.

In another aspect of the invention, a non-lithographic method comprisesforming interconnect structures in a dielectric layer; forming a layerof negative tone resist on exposed surfaces of the interconnectstructures and the dielectric layer; blanket-exposing the negative toneresist to energy; developing the negative tone resist to expose thesurface of the dielectric layer while maintaining a protective layer onthe surface of the interconnect structures; etching air gaps into thedielectric layer, while protecting the interconnect structures; andremoving the negative tone resist from the interconnect structures.

In another aspect of the invention, an intermediate structure comprisesa dielectric layer having air gaps between interconnect structures. Thestructure also includes a layer of negative tone spin-on organic polymerhaving a photoacid generator on exposed surfaces of the interconnectstructures. The photoacid generator leads to the negative tone spin-onorganic polymer being selectively removed over the dielectric layerafter exposure to energy. A capping material pinches off a perforatedhard mask layer over the polymer layer.

In yet another aspect of the invention, a structure comprises adielectric layer having gaps between metal interconnect structures and alayer of polymer having a photoacid generator on exposed surfaces of themetal interconnect structures. The structure also includes a pinched offperforated hard mask layer over the polymer layer.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The present invention is described in the detailed description whichfollows, in reference to the noted plurality of drawings by way ofnon-limiting examples of exemplary embodiments of the present invention,in which:

FIGS. 1-5 show intermediate structures and respective fabricationprocesses in accordance with a first aspect of the invention;

FIG. 6 shows a final structure and accompanying fabrication processes inaccordance with the first aspect of the invention;

FIGS. 7-11 show intermediate structures and respective fabricationprocesses in accordance with a second aspect of the invention; and

FIG. 12 shows a final structure and accompanying fabrication processesin accordance with the second aspect of the invention.

DETAILED DESCRIPTION

The present invention relates generally to an interconnect structure andmethod of fabricating the same and, more particularly, to a structurewith a self-aligned resist layer on a surface of the interconnects foruse in forming air gaps in an insulator material and method offabricating the same. In implementing the fabrication processes andstructures in accordance with the invention, a self-aligned resistmaterial is deposited on interconnects and/or other wires within thestructure. The self-aligned resist material protects the interconnectsduring the formation of air gaps within the insulator material. The airgaps effectively increase the insulative properties of the insulatormaterial.

First Aspect of the Invention

FIGS. 1-5 show intermediate structures and respective fabricationprocesses in accordance with a first aspect of the invention. Inparticular, FIG. 1 shows a structure comprising interconnects (generallydepicted as reference numeral 12) embedded within a dielectric(insulator) layer 10. In embodiments, the dielectric material 10 isSiO₂, low-k SiCOH, ultralow-k porous SiCOH, or other dielectricmaterial. In optional embodiments, a hard dielectric layer (hard mask)15 may be deposited and polished on the insulator material 10.

In embodiments, the interconnects 12 may be copper, lined with anothermetal 14 such as, for example, TaN or Ta. The interconnects 12 may beformed using conventional dual damascene fabrication processes such thatfurther explanation is not required herein for an understanding of theinvention.

In FIG. 2, a capping resist layer 16 is applied to the structure ofFIG. 1. In particular, the capping resist layer 16 may be a spin-onself-aligning resist layer such as, for example, an organic polymer. Inembodiments, the capping resist layer 16 is a class of organicphotoresist materials containing iodonium salts, which possesses aCu-catalyzed decomposition property.

In more particular embodiments, the capping resist layer 16 functions asa negative tone non-lithographic selective cap. Non-lithographic isrequired for absolute alignment, in the presence of overlay anddimensional control variations, such that the interconnects 12 remaincapped and the surfaces of the hard mask 15 are exposed in subsequentprocesses. In embodiments, the entire surface of all the interconnects12 remain capped in order to protect the interconnects during theformation of subsequent air gaps in the insulator layer 10. The cappingresist layer 16 may range in thickness from about 20 nm to 500 nm.

In more particular embodiments, the organic photoresist materials caninclude a photoacid generator (PAG) which can turn a material intoeither a negative or positive variety. In the embodiment describedherein, the PAG leads to the capping resist layer 16 being selectivelyremoved over the insulator material 10 after exposure to energy. Forsuch resist systems, the decomposition of the iodonium sensitizerproduces acid. This acid is used to activate the resist upon thermalheating which, in turn, prevents development of the resist. The mostcommon reaction would be cleavage of a t-butyl ester to produce acarboxlyic acid, which would be soluble in base. Alternatively amaterial like S-cap would liberate the free phenolic group, also solublein base.

As shown in FIG. 3, the capping resist layer 16 is exposed to energy(e.g., thermal, optical, e-beam) to induce an activation of the cappingresist layer 16 by acid generation, ring-breaking, or other mechanism.For example, the capping resist layer 16 can be flood-exposed to UV orDUV optical radiation. This will polymerize the capping resist layer 16over the Cu regions so that it can be developed off of the insulatorregions 10. In the case of PAG, mild heating will induce theself-aligned catalyzed activation. The amount of heat needed depends onthe protecting group, as should be understood by those of skill in theart.

In FIG. 4, the capping resist layer 16 is developed and, if necessary,baked, using conventional processes. This results in the capping resistlayer 16 selectively being removed from the exposed surface of theinsulator layer 10 and remaining on the metal surfaces of theinterconnects 12. The capping resist layer 16 protects the interconnects12 during subsequent etching processes.

In FIG. 5, perforations 17 are etched in the hard mask 15. To form theperforations, for example, a block copolymer nanotemplate can be formedover the hard mask 15. The block copolymer nanotemplate is a thin layerhaving features smaller than the minimal resolution features, e.g., thefeatures of the block copolymer nanotemplate are smaller than thespacing between the interconnects 12. The block copolymer nanotemplatemay be a material that self assembles into substantially uniformlyshaped and spaced holes or features. For example, the block copolymernanotemplate may be a self-assembled monolayer templated porous orpermeable film. The block copolymer nanotemplate may be e-beam, “uv” orthermally cured. An etching process is then performed to produceperforations in the hard mask 15. Further etching results in theformation of air gaps 20 in the insulator material. (See, for example,U.S. Publication No. 2008/0026541, the contents of which areincorporated by reference herein in its entirety.)

In embodiments, air gaps 20 can be formed directly in the insulatorlayer 10 without the need for a hard mask. The air gaps 20 can be formedusing any conventional etching process such as, for example, a RIE.

FIG. 6 shows a final structure and respective fabrication processes inaccordance with the invention. As shown in FIG. 6, the capping resistlayer 16 is removed by a solvent or ashing process, e.g., stripping orlifting off the capping resist layer 16. A capping layer 22 is depositedon the structure, which pinches off the perforations formed in the hardmask 15. In embodiments, the capping layer 22 is a SiCNH cap.

Second Aspect of the Invention

FIGS. 7-11 show intermediate structures and respective fabricfabrication processes in accordance with a second aspect of theinvention. In particular, FIG. 7 shows a structure comprisinginterconnects 12 embedded within a dielectric (insulator) layer 10. Inembodiments, the dielectric material 10 is SiO₂ or low-k SiCOHdielectric material. In embodiments, the interconnects 12 may be copperlined with another metal 14 such as, for example, TaN or Ta. Theinterconnects 12 may be formed using conventional dual damascenefabrication processes. In embodiments, a hard dielectric layer (hardmask) 15 may be deposited and polished on the insulator material 10.

In FIG. 7, a diffuse poisoning agent 20 is applied to the structure andpreferentially the interconnects 12. In embodiments, the poisoning agentmay be, for example, NH₃ or an amine gas or plasma. In embodiments, thepoisoning agent 20 is designed to remain on the exposed metal surfacesof the interconnects 12 to ensure that a subsequently applied resistlayer remains on the surface of the interconnects 12 when exposed to,for example, UV. In embodiments, the poisoning agent 20 is applied asNH₃, N₂/H₂ (forming gas), or other amine-producing gas or plasma towafers at room temperature or elevated temperature up to approximately400° C. in a vacuum chamber. For example, typical PECVD chambers withstandard NH₃/N₂ plasma preclean capability may be used.

In FIG. 8, the capping resist layer 16 is applied to the structure ofFIG. 7. In particular, the capping resist layer 16 may be a spin-onself-aligning resist layer such as, for example, an organic polymer. Inembodiments, the capping resist layer 16 is a class of organicphotoresist materials containing iodonium salts. In embodiments, thecapping resist layer 16 possesses a catalyzed decomposition property. Inmore particular embodiments, the capping resist layer 16 is a negativetone poison non-lithographic selective cap. The capping resist layer 16may range in thickness from about 20 nm to 500 nm.

As shown in FIG. 9, the capping resist layer 16 is exposed to energy(e.g., thermal, optical, e-beam) to induce a self-aligned catalyzedactivation of the capping resist layer 16 by acid generation,ring-breaking, or other mechanism. For example, the capping resist layer16 can be flood-exposed to UV or DUV optical radiation. This will induceself-aligned poisoning of the capping resist layer 16, e.g., cause achemical reaction of the poisoning on the exposed surface of the metalinterconnect 12. Typical exposures could be 100 C thermal bake forseveral minutes, or blanket DUV flood exposure at 193 nm wavelength at adose of ˜20 to ˜100 mJ/cm² (I need to check these numbers). Inembodiments, in this process, the entire surface of insulator layer 10is exposed; whereas, the interconnects 12 will remain capped to therebyprotect the interconnects 12 during subsequent etching processes.

In FIG. 10, the capping resist layer 16 is developed and, if necessary,baked, using conventional processes. This results in the capping resistlayer 16 being selectively removed from the surface of the insulatorlayer 10 and remaining on the metal surfaces of the interconnects 12.

In FIG. 11, perforations 17 are etched in the hard mask 15 as discussedabove. Also, air gaps 20 are formed in the insulator material 10.

FIG. 12 shows a final structure and respective fabrication processes inaccordance with the invention. As shown in FIG. 12, the capping resistlayer 16 is removed by a solvent or ashing process, e.g., stripping orlifting off the capping resist layer 16. A capping layer 22 is depositedon the structure, which pinches off the perforations formed in the hardmask 15. In embodiments, the capping layer 22 is a SiCNH cap.

The methods and structures as described above are used in thefabrication of integrated circuit chips. The resulting integratedcircuit chips can be distributed by the fabricator in raw wafer form(that is, as a single wafer that has multiple unpackaged chips), as abare die, or in a packaged form. In the latter case the chip is mountedin a single chip package (such as a plastic carrier, with the structuresof the invention) or in a multichip package (such as a ceramic carrierthat has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below, if applicable,are intended to include any structure, material, or act for performingthe function in combination with other claimed elements as specificallyclaimed. The description of the present invention has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the invention in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the invention.The embodiments were chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated. Accordingly, while the invention has beendescribed in terms of embodiments, those of skill in the art willrecognize that the invention can be practiced with modifications and inthe spirit and scope of the appended claims.

What is claimed is:
 1. A structure, comprising: a dielectric layerhaving gaps between metal interconnect structures formed in thedielectric layer; a hard mask layer, including perforations, formed overthe gaps between the metal interconnect structures; and a capping layerformed over the hard mask layer, including over the perforations,wherein an upper surface of the hard mask layer is substantiallycoplanar with upper surfaces of the metal interconnect structures. 2.The structure of claim 1, wherein: the gaps are air gaps; and thedielectric material is SiO₂, low-k SiCOH, or ultralow-k porous SiCOH. 3.The structure of claim 2, wherein: the metal interconnect structures arecopper; the copper is lined with TaN or Ta; and the perforations aresmaller than a spacing between adjacent metal interconnect structures.4. The structure of claim 3, wherein the air gaps are formed belowperforations of the perforated hard mask and are completely covered bythe perforated hard mask.
 5. The structure of claim 4, wherein thecapping layer is provided over the upper surfaces of the metalinterconnect structures.
 6. The structure of claim 5, wherein thecapping layer is a SiCNH cap.
 7. The structure of claim 6, wherein theair gaps extend from an upper surface of the dielectric layer into, butnot completely through, the dielectric layer.
 8. The structure of claim7, wherein at least one of the metal interconnect structures extendscompletely through the dielectric layer.
 9. The structure of claim 1,wherein a poisoning agent is formed on the upper surfaces of the metalinterconnect structures.
 10. The structure of claim 9, wherein in thepoisoning agent is NH₃, or an amine, or a plasma.
 11. The structure ofclaim 1, wherein capping layer completely covers the perforations in thehard mask layer.
 12. The structure of claim 11, wherein a poisoningagent is formed on the upper surfaces of the metal interconnectstructures.